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Rapid Design Space visualisation through hardware/software partitioning

Simon A. Spacey, Wayne Luk, Paul H.J. Kelly & Daniel Kuhn

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abstract This paper introduces the 3SP Design Space Exploration System. 3SP automatically quantifies acceleration opportunities for programs across a wide range of heterogeneous architectures to allow designers to identify promising implementation platforms before investing in a particular hardware/ software codesign. 3SP uses a novel program execution model to integrate comprehensive hardware characteristics including clock speed, number of execution units, issue rates, bandwidths and latencies with software program execution, parallelism, control and data flow measurements to estimate codesign performance for evaluating opportunities for hardware acceleration.
   
type conference paper (English)
   
keywords
   
name of conference 2009 5th Southern Conference on Programmable Logic (SPL) (São Carlos SP, Brazil)
date of conference 1-4-2009
title of proceedings 2009 5th Southern Conference on Programmable Logic (SPL)
page(s) 159-164
publisher Institute of Electrical and Electronics Engineers (IEEE)
ISBN 978-1-4244-3847-1
review external review
   
citation Spacey, S. A., Luk, W., Kelly, P. H., & Kuhn, D. (2009). Rapid Design Space visualisation through hardware/software partitioning. In 2009 5th Southern Conference on Programmable Logic (SPL), pp.159-164: Institute of Electrical and Electronics Engineers (IEEE). - ISBN 978-1-4244-3847-1.