Pionteck, T.T.PionteckStaake, ThorstenThorstenStaakeKabulepa, L.L.KabulepaGlesner, M.M.Glesner2023-04-132023-04-132004-05-23https://www.alexandria.unisg.ch/handle/20.500.14171/6776010.1109/ISCAS.2004.1329329This work presents the hardware design of a reconfigurable encryption/decryption engine for the Advanced Encryption Standard (AES) supporting all key lengths. The reconfigurable crypto-engine is integrated as a function unit in a 32 bit RISC processor and can operate in parallel with the standard ALU. Neither the pipeline structure nor the control logic for register forwarding and hazard detection are affected, allowing an easy integration into different RISC architectures. Reconfiguration can be done during runtime, allowing the processor to utilize the arithmetic components and memory elements of the crypto-unit for additional tasks like multiplication in the Galois Field GF(2/sup 8/) required for Reed-Solomon code generation. The RISC processor with the crypto-engine was synthesized using a 0.25 /spl mu/m CMOS technology.enconference paper