Rapid Design Space visualisation through hardware/software partitioning
ISBN
978-1-4244-3847-1
Type
conference paper
Date Issued
2009-04-01
Author(s)
Spacey, Simon A.
Luk, Wayne
Kelly, Paul H.J.
Kuhn, Daniel
Editor(s)
Obac Roda, Valentin
Abstract
This paper introduces the 3SP Design Space Exploration System. 3SP automatically quantifies acceleration opportunities for programs across a wide range of heterogeneous architectures to allow designers to identify promising implementation platforms before investing in a particular hardware/ software codesign. 3SP uses a novel program execution model to integrate comprehensive hardware characteristics including clock speed, number of execution units, issue rates, bandwidths and latencies with software program execution, parallelism, control and data flow measurements to estimate codesign performance for evaluating opportunities for hardware acceleration.
Language
English
HSG Classification
contribution to scientific community
Refereed
Yes
Book title
5th Southern Conference on Programmable Logic (SPL), 2009
Publisher
IEEE Computer Society
Publisher place
Piscataway, NJ
Start page
159
End page
164
Pages
6
Event Title
5th Southern Conference on Programmable Logic (SPL)
Event Location
São Carlos SP, Brazil
Event Date
01.-03.04.2009
Subject(s)
Division(s)
Eprints ID
60723